1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device in which protection from rupture of an Oxide-Nitride-Oxide (ONO) layer with a charge trap layer is enhanced, and a method of manufacturing the same.
2. Description of the Related Art
SONOS devices are considered to be very important as non-volatile memory devices. However, one significant problem with this type of devices is that for write and erase operations they require application of a high voltage that may ultimately destroy the ONO layer with the charge trap layer.
FIG. 1 is a cross-sectional view of a conventional SONOS device.
Referring to FIG. 1, in a conventional SONOS device an ONO structure 20 is formed on a silicon substrate 10. The ONO structure 20 includes a tunnel oxide layer 21, a silicon nitride layer 23, and a silicon oxide layer 25 for charge blocking. A conductive polysilicon layer is deposited on the ONO structure 20 to form a gate electrode 30. A source 41 and a drain 45 are formed on the substrate 10 adjacent to the gate electrode 30, thereby completing a transistor structure.
When a positive (+) voltage is applied to the gate electrode 30, electrons are transferred to the silicon surface. If a higher voltage is applied to the gate electrode 30, some of the electrons obtain sufficient energy and they move through the tunnel oxide layer 21 by FN tunneling. The electrons that move through the tunnel oxide layer 21 are trapped in the nitride layer 23 in the ONO structure 20. Therefore, during a write operation, negative charges 27 are trapped in the silicon nitride layer 23.
Because of the electrons trapped in the nitride layer 23, as the application of the high voltage to the gate electrode 30 continues, the voltage measurement increases to the transistor threshold voltage (Vth) causing the transistor to turn off, thereby terminating the program operation. In an attempt to improve such a program characteristic, prior art techniques have tried to form the ONO layer to be extremely thin such that the amount of electrons undergoing FN tunneling may be increased. A thin ONO structure 20, however, is easily ruptured at a high voltage. Furthermore, changing of the nitride layer characteristic has also been tried for improving the program characteristic.
Additionally, while during the program operation, the electrons in the region where the source 41 and the drain 45 overlap with the gate electrode 30 are transferred to the nitride layer 23, during an erase operation, such electrons may not easily escape to the channel region. This causes the overlap region to become unnecessarily charged with electrons. In turn, this phenomenon may cause the ONO layer 20 to be destroyed due to continual degradation of the ONO layer 20 by program-erase stress.